Fast, efficient and reliable testing is an important step in the design of ICs. Testing the overall design is typically performed by verifying the proper operation of certain logic structures of the IC. One of the logic structures that is considered to be difficult for verification is a FIFO element.
FIFOs are used commonly in ICs for buffering and flow control. In hardware form, a FIFO consists of a set of read and write pointers, storage and control logic. The storage may be RAM, flip-flops, latches or any other suitable form of storage. For FIFOs of non-trivial size, a dual-port SRAM is usually used where one port is used for writing and the other is used for reading. The write pointer holds the write address of the storage cell into which data should be written during the next write operation, and a read pointer holds the read address of the storage cell from which data should be read during the next read operation. The control logic generates the FIFO status flags that include full, empty, almost full, or almost empty. When the full flag is raised, no data can be written into the FIFO, and once the empty flag is raised no data can read from the FIFO.
There are two types of FIFOs in the related art: synchronous and asynchronous. A synchronous FIFO is a FIFO where the same clock is used for both reading and writing. An asynchronous FIFO uses different clocks for reading and writing. Asynchronous FIFOs introduce metastability issues, and thus a typical asynchronous FIFO implements a Gray code (or any other unit distance code) for the read and write pointers to ensure reliable flag generation.
Many defects and faults may be encountered during the operation of the FIFO structure due to a faulty design. The faults are generally classified as memory faults, control faults, and read and write logic faults. To detect these faults the FIFOs are tested during the design of an IC. In the related art, the FIFO tests are generally performed by simulating test vectors and explicit assertions of the status flags. Vector simulations comprise writing vectors to the FIFO being tested and reading vectors that are expected in response. Flag assertions tests include, for example, asserting the full flag and trying to write to the FIFO's memory. If the write succeeds then a FIFO fault is detected.
The prior art FIFO testing techniques require the user's intervention in specifying all FIFO structures that exist in the design. Moreover, such techniques require the user to specify, for each under-test FIFO, its structure and elements. In typical ICs, where the number of FIFO structures may be large, this is an inefficient and time-consuming task as well as being error prone.
Therefore, in the view of the limitations mentioned above, it would be advantageous to provide an efficient solution that would automatically recognize and verify FIFOs in IC designs.